工作忙,进度慢,再贴一段测试用的Verilog,就是做一个简单的导联模拟开关的切换
module ECG(/*CLK_in,*/Key_Hand,LED_CS,/*Hand_Auto,*/LED_out,Code_Tubes,Lead);
//input CLK_in;
input Key_Hand;
input LED_CS;
//input Hand_Auto;
output [7:0]Code_Tubes;
output [2:0]LED_out;
output [8:0]Lead;
reg [3:0]Standard_Leads;
reg [7:0]Code_Tubes_Buffer;
reg [8:0]Lead;
//定义12导联及自检
parameter I = 4'd1;
parameter II = 4'd2;
parameter III = 4'd3;
parameter aVR = 4'd4;
parameter aVL = 4'd5;
parameter aVF = 4'd6;
parameter V1 = 4'd7;
parameter V2 = 4'd8;
parameter V3 = 4'd9;
parameter V4 = 4'd10;
parameter V5 = 4'd11;
parameter V6 = 4'd12;
parameter Test = 4'd13;
parameter Reset = 4'd0;
//数码管位定义
parameter char_0 = 8'b10110111;
parameter char_1 = 8'b10000100;
parameter char_2 = 8'b00101111;
parameter char_3 = 8'b10001111;
parameter char_4 = 8'b10011100;
parameter char_5 = 8'b10011011;
parameter char_6 = 8'b10111011;
parameter char_7 = 8'b10000110;
parameter char_8 = 8'b10111111;
parameter char_9 = 8'b10011111;
parameter char_A = 8'b10111110;
parameter char_B = 8'b10111001;
parameter char_C = 8'b00110011;
parameter char_D = 8'b10101101;//
parameter char_E = 8'b00111011;
always@(negedge Key_Hand)
begin
case (Standard_Leads)
Reset :Standard_Leads <= I;
I :Standard_Leads <= II;
II :Standard_Leads <= III;
III :Standard_Leads <= aVR;
aVR :Standard_Leads <= aVL;
aVL :Standard_Leads <= aVF;
aVF :Standard_Leads <= V1;
V1 :Standard_Leads <= V2;
V2 :Standard_Leads <= V3;
V3 :Standard_Leads <= V4;
V4 :Standard_Leads <= V5;
V5 :Standard_Leads <= V6;
V6 :Standard_Leads <= Test;
Test :Standard_Leads <= Reset;
default :;
endcase
end
//是否打开LED显示开关,如果没有打开则关闭所有数码管,用于节能
assign Code_Tubes = (!LED_CS)? Code_Tubes_Buffer : 8'b00000000;
always@(Standard_Leads)
begin
case (Standard_Leads)
Reset :Code_Tubes_Buffer <= char_0;
I :Code_Tubes_Buffer <= char_1;
II :Code_Tubes_Buffer <= char_2;
III :Code_Tubes_Buffer <= char_3;
aVR :Code_Tubes_Buffer <= char_4;
aVL :Code_Tubes_Buffer <= char_5;
aVF :Code_Tubes_Buffer <= char_6;
V1 :Code_Tubes_Buffer <= char_7;
V2 :Code_Tubes_Buffer <= char_8;
V3 :Code_Tubes_Buffer <= char_9;
V4 :Code_Tubes_Buffer <= char_A;
V5 :Code_Tubes_Buffer <= char_B;
V6 :Code_Tubes_Buffer <= char_C;
Test :Code_Tubes_Buffer <= char_D;
default :;
endcase
end
//导联切换,Lead[u5(CBA)u6(CBA)u4(CBA)]
always@(Standard_Leads)
begin
case (Standard_Leads)
Reset [s:10]ead <= 9'b010111000;
I [s:10]ead <= 9'b111100000;
II [s:10]ead <= 9'b001100000;
III [s:10]ead <= 9'b001110000;
aVR [s:10]ead <= 9'b101011000;
aVL [s:10]ead <= 9'b111000000;
aVF [s:10]ead <= 9'b001001000;
V1 [s:10]ead <= 9'b000000000;
V2 [s:10]ead <= 9'b000000001;
V3 [s:10]ead <= 9'b000000010;
V4 [s:10]ead <= 9'b000000011;
V5 [s:10]ead <= 9'b000000100;
V6 [s:10]ead <= 9'b000000101;
Test [s:10]ead <= 9'b011111000;
default :;
endcase
end
endmodule