X86平台框架和电源状态
之前分享了一个工厂测试问题，感觉大家对PC这块还是蛮感兴趣的，分享些前置学习资料，顺便打个广告，我司目前正在招３年以上的X86 EE，薪资好说，感兴趣可以私聊我内推；
先分享一个老平台Skylake-S的硬件框架图：
然后就是PC的系统电源状态和CPU状态（14th MTL之前的）：
System Power States
S0:working state: the processor is executing instructions. The system is completely operation, fully powered and completely retains the context.
S1: standby powered on suspend: system is in standby mode, this state has low wakeup latency on resume. All Hardware & Processor context is maintained.
S2: power standby : Processor loses power and processor context and contents of the cache are lost.
S3: standby suspend to RAM: system is off but context is saved to RAM. Processor & Hardware context, cache contents, and chipset context are lost. System memory is put into self_refresh.
S4: hibernate suspend to disk: system is off but context is saved to disk. When the system transitions to the working state, the OS is resumed without a system re_boot.
（SLP_S4#——S4 Sleep Control. This signal is for power plane control. When asserted (low), it will shut-off power to all non-critical systems in S4 (Suspend to Disk) or S5 (Soft Off) states.）
S5: soft off: system is off. OS re_boot when the system transitions to the working state. All power is shut off except for the logic required to restart.
（SLP_S5#——This signal is for power plane control. When asserted (low), it will shut-off power to all non-critical systems in S5 (Soft Off) states.）
CPU Power states
C0:normal working state: the processor is executing instructions. CPU fully turned on.
C1:CPU Halt state. No instructions are executed. This state has the lowest latency on resume and contributes minimum power savings.
C2: stop grant caches snoopable: stop grant or cache snoopable CPU state. This state offers more power savings but has a higher latency on resume than the C1 state.
C3: Deep Sleep: processor is put into stop grant state. Caches are still snoopable. The hyper transport link may be disconnected and put into a low power state. System memory may be put into self-refresh.
C4: Deeper Sleep: similar with C3.but the core voltage low than 1.0V, the memory cache contents is reduced.
C5: Enhanced Deeper Sleep: Reduces CPU voltage even more and turns off the memory cache.
C6: Deep Power Down: Reduces the CPU internal voltage to any value, including 0 V. turns off the memory cache. Don't save CPU context.
| Mode | Name | What it does | CPUs |
| C0 | Operating State | CPU fully turned on | All CPUs |
| C1 | Halt | Stops CPU main internal clocks via software; bus interface unit and APIC are kept running at full speed. | 486DX4 and above |
| C1E | Enhanced Halt | Stops CPU main internal clocks via software and reduces CPU voltage; bus interface unit and APIC are kept running at full speed. | All socket 775 CPUs |
| C1E | — | Stops all CPU internal clocks. | Turion 64, 65-nm Athlon X2 and Phenom CPUs |
| C2 | Stop Grant | Stops CPU main internal clocks via hardware; bus interface unit and APIC are kept running at full speed. | 486DX4 and above |
| C2 | Stop Clock | Stops CPU internal and external clocks via hardware | Only 486DX4, Pentium, Pentium MMX, K5, K6, K6-2, K6-III |
| C2E | Extended Stop Grant | Stops CPU main internal clocks via hardware and reduces CPU voltage; bus interface unit and APIC are kept running at full speed. | Core 2 Duo and above (Intel only) |
| C3 | Sleep | Stops all CPU internal clocks | Pentium II, Athlon and above, but not on Core 2 Duo E4000 and E6000 |
| C3 | Deep Sleep | Stops all CPU internal and external clocks | Pentium II and above, but not on Core 2 Duo E4000 and E6000; Turion 64 |
| C3 | AltVID | Stops all CPU internal clocks and reduces CPU voltage | AMD Turion 64 |
| C4 | Deeper Sleep | Reduces CPU voltage | Pentium M and above, but not on Core 2 Duo E4000 and E6000 series; AMD Turion 64 |
| C4E/C5 | Enhanced Deeper Sleep | Reduces CPU voltage even more and turns off the memory cache | Core Solo, Core Duo and 45-nm mobile Core 2 Duo only |
| C6 | Deep Power Down | Reduces the CPU internal voltage to any value, including 0 V | 45-nm mobile Core 2 Duo only |
14th MTL平台的状态：
分为以下四个部分；
Core States：
Package C-States：
Graphics Companion Die (GC) Power States：
Type C Sub-System (TCSS) States
暂时资料保密，等平台发布后再共享给大家
[ 修改于3年3个月前 - 2023/07/31 21:10:08 ]