用1bit DAC更简单
或者干脆PWM闭环推大功率管做D类功放

1bit verilog 例子
已经modelsim过关


module dac(clk,nrst,data,dout);

`define wl 17

input clk,nrst;
input [`wl-2:0]data;
output dout;

reg [`wl-1:0]acc;

always @ (nrst or posedge clk)
begin
    if(!nrst)
    begin
        acc <= `wl'b0;
    end
    else
    begin
        acc <= acc[`wl-2:0] + data;
    end
end

assign dout = acc[`wl-1];

endmodule